MC68HC908GR16 Datasheet, PDF (261/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Timer Interface Module (TIM)
I/O Registers
Table 18-3. Mode, Edge, and Level Selection
MSxB:MSxA ELSxB:ELSxA
Mode
Configuration
X0
00
Output
Pin under port control; initial output level high
X1
00
preset
Pin under port control; initial output level low
00
01
Capture on rising edge only
00
10
Input
capture
Capture on falling edge only
00
11
Capture on rising or falling edge
01
01
Toggle output on compare
01
10
Output compare
or PWM
Clear output on compare
01
11
Set output on compare
1X
01
Buffered output Toggle output on compare
1X
10
compare
Clear output on compare
or buffered
1X
11
PWM
Set output on compare
NOTE:
NOTE:
Before enabling a TIM channel register for input capture operation, make sure that
the PTD/TCHx pin is stable for at least two bus clocks.
TOVx — Toggle On Overflow Bit
When channel x is an output compare channel, this read/write bit controls the
behavior of the channel x output when the TIM counter overflows. When
channel x is an input capture channel, TOVx has no effect. Reset clears the
TOVx bit.
1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.
When TOVx is set, a TIM counter overflow takes precedence over a channel x
output compare if both occur at the same time.
CHxMAX — Channel x Maximum Duty Cycle Bit
When the TOVx bit is at logic 1, setting the CHxMAX bit forces the duty cycle of
buffered and unbuffered PWM signals to 100%. As Figure 18-12 shows, the
CHxMAX bit takes effect in the cycle after it is set or cleared. The output stays
at the 100% duty cycle level until the cycle after CHxMAX is cleared.
OVERFLOW
OVERFLOW
TCHx
PERIOD
OVERFLOW
OVERFLOW
OVERFLOW
CHxMAX
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
OUTPUT
COMPARE
Figure 18-12. CHxMAX Latency
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Timer Interface Module (TIM)
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Data Sheet
261