MC68HC908GR16 Datasheet, PDF (234/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
(See 16.7.2 Mode Fault Error.) For the state of the SS pin to set the MODF flag,
the MODFEN bit in the SPSCK register must be set. If the MODFEN bit is low for
an SPI master, the SS pin can be used as a general-purpose I/O under the control
of the data direction register of the shared I/O port. With MODFEN high, it is an
input-only pin to the SPI regardless of the state of the data direction register of the
shared I/O port.
The CPU can always read the state of the SS pin by configuring the appropriate
pin as an input and reading the port data register. See Table 16-3.
Table 16-3. SPI Configuration
SPE
0
1
1
1
SPMSTR
X⁽¹⁾⁾
0
1
1
MODFEN
X
X
0
1
SPI Configuration
Not enabled
Slave
Master without MODF
Master with MODF
1. X = Don’t care
State of SS Logic
General-purpose I/O; SS ignored by SPI
Input-only to SPI
General-purpose I/O; SS ignored by SPI
Input-only to SPI
16.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the
port output buffers. It is internally connected to V_SS as shown in Table 16-1.
16.13 I/O Registers
Three registers control and monitor SPI operation:
• SPI control register (SPCR)
• SPI status and control register (SPSCR)
• SPI data register (SPDR)
16.13.1 SPI Control Register
The SPI control register:
• Enables SPI module interrupt requests
• Configures the SPI module as master or slave
• Selects serial clock polarity and phase
• Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
• Enables the SPI module
Data Sheet
234
Serial Peripheral Interface (SPI) Module
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MC68HC908GR16 — Rev. 1.0
MOTOROLA