MC68HC908GR16 Datasheet, PDF (229/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
Interrupts
NOTE:
When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0) and later
unselected (SS is at logic 1) even if no SPSCK is sent to that slave. This happens
because SS at logic 0 indicates the start of the transmission (MISO driven out with
the value of MSB) for CPHA = 0. When CPHA = 1, a slave can be selected and
then later unselected with no transmission occurring. Therefore, MODF does not
occur since a transmission was never begun.
In a slave SPI (MSTR = 0), the MODF bit generates an SPI receiver/error CPU
interrupt request if the ERRIE bit is set. The MODF bit does not clear the SPE bit
or reset the SPI in any way. Software can abort the SPI transmission by clearing
the SPE bit of the slave.
A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK clocks, even if it
was already in the middle of a transmission.
To clear the MODF flag, read the SPSCR with the MODF bit set and then write to
the SPCR register. This entire clearing mechanism must occur with no MODF
condition existing or else the flag is not cleared.
16.8 Interrupts
Four SPI status flags can be enabled to generate CPU interrupt requests. See
Table 16-2.
Table 16-2. SPI Interrupts
Flag
SPTE
Transmitter empty
SPRF
Receiver full
OVRF
Overflow
MODF
Mode fault
Request
SPI transmitter CPU interrupt request
(SPTIE = 1, SPE = 1)
SPI receiver CPU interrupt request
(SPRIE = 1)
SPI receiver/error interrupt request
(ERRIE = 1)
SPI receiver/error interrupt request
(ERRIE = 1)
Reading the SPI status and control register with SPRF set and then reading the
receive data register clears SPRF. The clearing mechanism for the SPTE flag is
always just a write to the transmit data register.
The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag to generate
transmitter CPU interrupt requests, provided that the SPI is enabled (SPE = 1).
The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to generate
receiver CPU interrupt requests, regardless of the state of the SPE bit. See
Figure 16-12.
The error interrupt enable bit (ERRIE) enables both the MODF and OVRF bits to
generate a receiver/error CPU interrupt request.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Serial Peripheral Interface (SPI) Module
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Data Sheet
229