MC68HC908GR16 Datasheet, PDF (268/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
19.2.2.5 Break Flag Control Register
The break control register (BFCR) contains a bit that enables software to clear
status bits while the MCU is in a break state.
Address: $FE03
Bit 7
6
5
4
3
2
1
Bit 0
Read:
BCFE
R
R
R
R
R
R
R
Write:
Reset: 0
R = Reserved
Figure 19-8. Break Flag Control Register (BFCR)
BCFE — Break Clear Flag Enable Bit
This read/write bit enables software to clear status bits by accessing status
registers while the MCU is in a break state. To clear status bits during the break
state, the BCFE bit must be set.
1 = Status bits clearable during break
0 = Status bits not clearable during break
19.2.3 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power- consumption standby
modes. If enabled, the break module will remain enabled in wait and stop modes.
However, since the internal address bus does not increment in these modes, a
break interrupt will never be triggered.
19.3 Monitor ROM (MON)
This section describes the monitor ROM (MON) and the monitor mode entry
methods. The monitor ROM allows complete testing of the microcontroller unit
(MCU) through a single-wire interface with a host computer. Monitor mode entry
can be achieved without use of the higher test voltage, V_TST, as long as vector
addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements
for in-circuit programming.
Features of the monitor ROM include:
• Normal user-mode pin functionality
• One pin dedicated to serial communication between monitor read-only
memory (ROM) and host computer
• Standard mark/space non-return-to-zero (NRZ) communication with host
computer
• Standard communication baud rate (9,600 @ 2.4576-MHz bus frequency)
Data Sheet
268
Development Support
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MC68HC908GR16 — Rev. 1.0
MOTOROLA