MC68HC908GR16 Datasheet, PDF (228/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Serial Peripheral Interface (SPI) Module
16.7.2 Mode Fault Error
Setting the SPMSTR bit selects master mode and configures the SPSCK and
MOSI pins as outputs and the MISO pin as an input. Clearing SPMSTR selects
slave mode and configures the SPSCK and MOSI pins as inputs and the MISO pin
as an output. The mode fault bit, MODF, becomes set any time the state of the
slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:
• The SS pin of a slave SPI goes high during a transmission
• The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be
set. Clearing the MODFEN bit does not clear the MODF flag but does prevent
MODF from being set again after MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable
bit (ERRIE) is also set. The SPRF, MODF, and OVRF interrupts share the same
CPU interrupt vector. (See Figure 16-12.) It is not possible to enable MODF or
OVRF individually to generate a receiver/error CPU interrupt request. However,
leaving MODFEN low prevents MODF from being set.
In a master SPI with the mode fault enable bit (MODFEN) set, the mode fault flag
(MODF) is set if SS goes to logic 0. A mode fault in a master SPI causes the
following events to occur:
• If ERRIE = 1, the SPI generates an SPI receiver/error CPU interrupt request.
• The SPE bit is cleared.
• The SPTE bit is set.
• The SPI state counter is cleared.
• The data direction register of the shared I/O port regains control of port
drivers.
NOTE:
To prevent bus contention with another master SPI after a mode fault error, clear
all SPI bits of the data direction register of the shared I/O port before enabling the
SPI.
When configured as a slave (SPMSTR = 0), the MODF flag is set if SS goes high
during a transmission. When CPHA = 0, a transmission begins when SS goes low
and ends once the incoming SPSCK goes back to its idle level following the shift
of the eighth data bit. When CPHA = 1, the transmission begins when the SPSCK
leaves its idle level and SS is already low. The transmission continues until the
SPSCK returns to its idle level following the shift of the last data bit. See
16.5 Transmission Formats.
NOTE:
Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit has no
function when SPE = 0. Reading SPMSTR when MODF = 1 shows the difference
between a MODF occurring when the SPI is a master and when it is a slave.
Data Sheet
228
Serial Peripheral Interface (SPI) Module
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MC68HC908GR16 — Rev. 1.0
MOTOROLA