MC68HC908GR16 Datasheet, PDF (127/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
LVI Status Register
11.3.1 Polled LVI Operation
In applications that can operate at V_DD levels below the V_TRIPF level, software can
monitor V_DD by polling the LVIOUT bit. In the configuration register, the LVIPWRD
bit must be at logic 0 to enable the LVI module, and the LVIRSTD bit must be at
logic 1 to disable LVI resets.
11.3.2 Forced Reset Operation
In applications that require V_DD to remain above the V_TRIPF level, enabling LVI
resets allows the LVI module to reset the MCU when V_DD falls below the V_TRIPF
level. In the configuration register, the LVIPWRD and LVIRSTD bits must be at
logic 0 to enable the LVI module and to enable LVI resets.
11.3.3 Voltage Hysteresis Protection
Once the LVI has triggered (by having V_DD fall below V_TRIPF), the LVI will maintain
a reset condition until V_DD rises above the rising trip point voltage, V_TRIPR. This
prevents a condition in which the MCU is continually entering and exiting reset if
V_DD is approximately equal to V_TRIPF. V_TRIPR is greater than V_TRIPF by the
hysteresis voltage, V_HYS.
11.3.4 LVI Trip Selection
The LVI5OR3 bit in the configuration register selects whether the LVI is configured
for 5-V or 3-V protection.
NOTE:
The microcontroller is guaranteed to operate at a minimum supply voltage. The trip
point (V_TRIPF [5 V] or V_TRIPF [3 V]) may be lower than this. See Section 20.
Electrical Specifications for the actual trip point voltages.
11.4 LVI Status Register
The LVI status register (LVISR) indicates if the V_DD voltage was detected below
the V_TRIPF level.
Address: $FE0C
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
0
0
0
0
0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 11-3. LVI Status Register (LVISR)
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Low-Voltage Inhibit (LVI)
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Data Sheet
127