MC68HC908GR16 Datasheet, PDF (180/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Enhanced Serial Communications Interface (ESCI) Module
14.8.3 ESCI Control Register 3
ESCI control register 3 (SCC3):
• Stores the ninth ESCI data bit received and the ninth ESCI data bit to be
transmitted.
• Enables these interrupts:
– Receiver overrun
– Noise error
– Framing error
– Parity error
Address:
Read:
Write:
Reset:
$0015
Bit 7
R8
U
6
5
T8
R
0
0
= Unimplemented
4
3
2
1
Bit 0
R
ORIE
NEIE
FEIE
PEIE
0
0
0
0
0
R
= Reserved U = Unaffected
Figure 14-12. ESCI Control Register 3 (SCC3)
R8 — Received Bit 8
When the ESCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8)
of the received character. R8 is received at the same time that the SCDR
receives the other 8 bits.
When the ESCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit
7). Reset has no effect on the R8 bit.
T8 — Transmitted Bit 8
When the ESCI is transmitting 9-bit characters, T8 is the read/write ninth bit
(bit 8) of the transmitted character. T8 is loaded into the transmit shift register at
the same time that the SCDR is loaded into the transmit shift register. Reset
clears the T8 bit.
ORIE — Receiver Overrun Interrupt Enable Bit
This read/write bit enables ESCI error CPU interrupt requests generated by the
receiver overrun bit, OR. Reset clears ORIE.
1 = ESCI error CPU interrupt requests from OR bit enabled
0 = ESCI error CPU interrupt requests from OR bit disabled
NEIE — Receiver Noise Error Interrupt Enable Bit
This read/write bit enables ESCI error CPU interrupt requests generated by the
noise error bit, NE. Reset clears NEIE.
1 = ESCI error CPU interrupt requests from NE bit enabled
0 = ESCI error CPU interrupt requests from NE bit disabled
Data Sheet
180
MC68HC908GR16 — Rev. 1.0
Enhanced Serial Communications Interface (ESCI) Module
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