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MC68HC908GR16 Datasheet, PDF (198/310 Pages) Motorola, Inc – Microcontrollers
Freescale Semiconductor, Inc.
System Integration Module (SIM)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$FE00
Break Status Register Read:
R
(BSR) Write:
R
R
R
R
SBSW
R
Note(1)
R
See page 212. Reset:
0
0
0
0
0
0
0
0
1. Writing a logic 0 clears SBSW.
SIM Reset Status Register Read: POR
PIN
COP
ILOP
ILAD MODRST LVI
0
$FE01
(SRSR) Write:
See page 213. POR:
1
0
0
0
0
0
0
0
Break Flag Control Register Read: BCFE
R
R
R
R
R
R
R
$FE03
(BFCR) Write:
See page 214. Reset:
0
Interrupt Status Register 1 Read: IF6
IF5
IF4
IF3
IF2
IF1
0
0
$FE04
(INT1) Write: R
R
R
R
R
R
R
R
See page 208. Reset:
0
0
0
0
0
0
0
0
Interrupt Status Register 2 Read: IF14
IF13
IF12
IF11
IF10
IF9
IF8
IF7
$FE05
(INT2) Write: R
R
R
R
R
R
R
R
See page 208. Reset:
0
0
0
0
0
0
0
0
Interrupt Status Register 3 Read:
0
$FE06
(INT3) Write: R
See page 208. Reset:
0
0
IF20
IF19
IF18
IF17
IF16
IF15
R
R
R
R
R
R
R
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 15-3. SIM I/O Register Summary
15.2 SIM Bus Clock Control and Generation
The bus clock generator provides system clock signals for the CPU and peripherals
on the MCU. The system clocks are generated from an incoming clock, CGMOUT,
as shown in Figure 15-4. This clock originates from either an external oscillator or
from the on-chip PLL.
15.2.1 Bus Timing
In user mode, the internal bus frequency is either the crystal oscillator output
(CGMXCLK) divided by four or the PLL output (CGMVCLK) divided by four.
15.2.2 Clock Startup from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module generates a
reset, the clocks to the CPU and peripherals are inactive and held in an inactive
phase until after the 4096 CGMXCLK cycle POR timeout has completed. The RST
pin is driven low by the SIM during this entire period. The IBUS clocks start upon
completion of the timeout.
Data Sheet
198
System Integration Module (SIM)
For More Information On This Product,
Go to: www.freescale.com
MC68HC908GR16 — Rev. 1.0
MOTOROLA