MC68HC908GR16 Datasheet, PDF (280/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
V_DD
4096 + 32 CGMXCLK CYCLES
RST
FROM HOST
PA0
5
FROM MCU
1
4
1
1
2
4
1
Notes:
1 = Echo delay, 2 bit times
2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte
5 = Wait until a clock is stable (if PLL is enabled) and the monitor ROM runs
Figure 19-18. Monitor Mode Entry Timing
To determine whether the security code entered is correct, check to see if bit 6 of
RAM address $40 is set. If it is, then the correct security code has been entered
and FLASH can be accessed.
If the security sequence fails, the device should be reset by a power-on reset and
brought up in monitor mode to attempt another entry. After failing the security
sequence, the FLASH module can also be mass erased by executing an erase
routine that was downloaded into internal RAM. The mass erase operation clears
the security code locations so that all eight security bytes become $FF (blank).
Data Sheet
280
Development Support
For More Information On This Product,
Go to: www.freescale.com
MC68HC908GR16 — Rev. 1.0
MOTOROLA