MC68HC908GR16 Datasheet, PDF (122/310 Pages) Motorola, Inc – Microcontrollers

Low-Power Modes
Freescale Semiconductor, Inc.
OSCENINSTOP bit in the CONFIG2 register. The timebase module can be used
in this mode to generate a periodic wakeup from stop mode.
If the oscillator has not been enabled to operate in stop mode, the timebase module
will not be active during stop mode. In stop mode, the timebase register is not
accessible by the CPU.
If the timebase functions are not required during stop mode, reduce the power
consumption by stopping the timebase before enabling the STOP instruction.
10.14 Exiting Wait Mode
These events restart the CPU clock and load the program counter with the reset
vector or with an interrupt vector:
• External reset — A logic 0 on the RST pin resets the MCU and loads the
program counter with the contents of locations $FFFE and $FFFF.
• External interrupt — A high-to-low transition on an external interrupt pin
(IRQ pin) loads the program counter with the contents of locations: $FFFA
and $FFFB; IRQ pin.
• Break interrupt — In emulation mode, a break interrupt loads the program
counter with the contents of $FFFC and $FFFD.
• Computer operating properly (COP) module reset — A timeout of the COP
counter resets the MCU and loads the program counter with the contents of
$FFFE and $FFFF.
• Low-voltage inhibit (LVI) module reset — A power supply voltage below the
V_TRIPF voltage resets the MCU and loads the program counter with the
contents of locations $FFFE and $FFFF.
• Clock generator module (CGM) interrupt — A CPU interrupt request from
the ICG loads the program counter with the contents of $FFF8 and $FFF9.
• Keyboard interrupt (KBI) module — A CPU interrupt request from the KBI
module loads the program counter with the contents of $FFE0 and $FFE1.
• Timer 1 interface (TIM1) module interrupt — A CPU interrupt request from
the TIM1 loads the program counter with the contents of:
– $FFF2 and $FFF3; TIM1 overflow
– $FFF4 and $FFF5; TIM1 channel 1
– $FFF6 and $FFF7; TIM1 channel 0
• Timer 2 interface (TIM2) module interrupt — A CPU interrupt request from
the TIM2 loads the program counter with the contents of:
– $FFEC and $FFED; TIM2 overflow
– $FFF0 and $FFF1; TIM2 channel 0
• Serial peripheral interface (SPI) module interrupt — A CPU interrupt request
from the SPI loads the program counter with the contents of:
– $FFE8 and $FFE9; SPI transmitter
– $FFEA and $FFEB; SPI receiver
Data Sheet
122
Low-Power Modes
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MC68HC908GR16 — Rev. 1.0
MOTOROLA