MC68HC908GR16 Datasheet, PDF (263/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Data Sheet — MC68HC908GR16
Section 19. Development Support
19.1 Introduction
This section describes the break module, the monitor read-only memory (MON),
and the monitor mode entry methods.
19.2 Break Module (BRK)
This subsection describes the break module. The break module can generate a
break interrupt that stops normal program flow at a defined address to enter a
background program.
Features of the break module include:
• Accessible input/output (I/O) registers during the break Interrupt
• Central processor unit (CPU) generated break interrupts
• Software-generated break interrupts
• Computer operating properly (COP) disabling during break interrupts
19.2.1 Functional Description
When the internal address bus matches the value written in the break address
registers, the break module issues a breakpoint signal (BKPT) to the system
integration module (SIM). The SIM then causes the CPU to load the instruction
register with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode).
The following events can cause a break interrupt to occur:
• A CPU generated address (the address in the program counter) matches
the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and control
register.
When a CPU generated address matches the contents of the break address
registers, the break interrupt begins after the CPU completes its current instruction.
A return-from-interrupt instruction (RTI) in the break routine ends the break
interrupt and returns the microcontroller unit (MCU) to normal operation.
Figure 19-1 shows the structure of the break module.
Figure 19-2 provides a summary of the I/O registers.
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Development Support
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Data Sheet
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