MC68HC908GR16 Datasheet, PDF (146/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Resets and Interrupts
13.2.3.1 Power-On Reset (POR)
A power-on reset (POR) is an internal reset caused by a positive transition on the
V_DD pin. V_DD at the POR must go below V_POR to reset the MCU. This distinguishes
between a reset and a POR. The POR is not a brown-out detector, low-voltage
detector, or glitch detector.
A power-on reset:
• Holds the clocks to the central processor unit (CPU) and modules inactive
for an oscillator stabilization delay of 4096 CGMXCLK cycles
• Drives the RST pin low during the oscillator stabilization delay
• Releases the RST pin 32 CGMXCLK cycles after the oscillator stabilization
delay
• Releases the CPU to begin the reset vector sequence 64 CGMXCLK cycles
after the oscillator stabilization delay
• Sets the POR and LVI bits in the SIM reset status register and clears all
other bits in the register
OSC1
PORRST⁽¹⁾
CGMXCLK
CGMOUT
RST PIN
4096
32
CYCLES CYCLES
1. PORRST is an internally generated power-on reset pulse.
Figure 13-1. Power-On Reset Recovery
13.2.3.2 Computer Operating Properly (COP) Reset
A computer operating properly (COP) reset is an internal reset caused by an
overflow of the COP counter. A COP reset sets the COP bit in the SIM reset status
register.
To clear the COP counter and prevent a COP reset, write any value to the COP
control register at location $FFFF.
Data Sheet
146
Resets and Interrupts
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MC68HC908GR16 — Rev. 1.0
MOTOROLA