MC68HC908GR16 Datasheet, PDF (118/310 Pages) Motorola, Inc – Microcontrollers

Low-Power Modes
Freescale Semiconductor, Inc.
10.3 Break Module (BRK)
10.3.1 Wait Mode
If enabled, the break (BRK) module is active in wait mode. In the break routine, the
user can subtract one from the return address on the stack if the SBSW bit in the
break status register is set.
10.3.2 Stop Mode
The break module is inactive in stop mode. A break interrupt causes exit from stop
mode and sets the SBSW bit in the break status register. The STOP instruction
does not affect break module register states.
10.4 Central Processor Unit (CPU)
10.4.1 Wait Mode
The WAIT instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling
interrupts. After exit from wait mode by interrupt, the I bit remains clear. After
exit by reset, the I bit is set.
• Disables the CPU clock
10.4.2 Stop Mode
The STOP instruction:
• Clears the interrupt mask (I bit) in the condition code register, enabling
external interrupts. After exit from stop mode by external interrupt, the I bit
remains clear. After exit by reset, the I bit is set.
• Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
10.5 Clock Generator Module (CGM)
10.5.1 Wait Mode
The clock generator module (CGM) remains active in wait mode. Before entering
wait mode, software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive applications
can disengage the PLL without turning it off. Applications that require the PLL to
wake the MCU from wait mode also can deselect the PLL output without turning off
the PLL.
Data Sheet
118
Low-Power Modes
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MC68HC908GR16 — Rev. 1.0
MOTOROLA