MC68HC908GR16 Datasheet, PDF (266/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
19.2.2.1 Break Status and Control Register
The break status and control register (BRKSCR) contains break module enable
and status bits.
Address: $FE0B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
0
BRKE BRKA
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-3. Break Status and Control Register (BRKSCR)
BRKE — Break Enable Bit
This read/write bit enables breaks on break address register matches. Clear
BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.
1 = Breaks enabled on 16-bit address match
0 = Breaks disabled
BRKA — Break Active Bit
This read/write status and control bit is set when a break address match occurs.
Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a
logic 0 to it before exiting the break routine. Reset clears the BRKA bit.
1 = Break address match
0 = No break address match
19.2.2.2 Break Address Registers
The break address registers (BRKH and BRKL) contain the high and low bytes of
the desired breakpoint address. Reset clears the break address registers.
Address: $FE09
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-4. Break Address Register High (BRKH)
Address: $FE0A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Write:
Reset: 0
0
0
0
0
0
0
0
Figure 19-5. Break Address Register Low (BRKL)
Data Sheet
266
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MC68HC908GR16 — Rev. 1.0
MOTOROLA