MC68HC908GR16 Datasheet, PDF (139/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Input/Output Ports (PORTS)
Port D
T2CH1 and T2CH0 — Timer 2 Channel I/O Bits
The PTD6/T2CH0–PTD7/T2CH1 pins are the TIM2 input capture/output
compare pins. The edge/level select bits, ELSxB and ELSxA, determine
whether the PTD6/T2CH0–PTD7/T2CH1 pins are timer channel I/O pins or
general-purpose I/O pin. See Section 18. Timer Interface Module (TIM).
T1CH1 and T1CH0 — Timer 1 Channel I/O Bits
The PTD4/T1CH0–PTD5/T1CH1 pins are the TIM1 input capture/output
compare pins. The edge/level select bits, ELSxB and ELSxA, determine
whether the PTD4/T1CH0–PTD5/T1CH1 pins are timer channel I/O pins or
general-purpose I/O pins. See Section 18. Timer Interface Module (TIM).
SPSCK — SPI Serial Clock
The PTD3/SPSCK pin is the serial clock input of the SPI module. When the SPE
bit is clear, the PTD3/SPSCK pin is available for general-purpose I/O.
MOSI — Master Out/Slave In
The PTD2/MOSI pin is the master out/slave in terminal of the SPI module. When
the SPE bit is clear, the PTD2/MOSI pin is available for general-purpose I/O.
MISO — Master In/Slave Out
The PTD1/MISO pin is the master in/slave out terminal of the SPI module. When
the SPI enable bit, SPE, is clear, the SPI module is disabled, and the PTD0/SS
pin is available for general-purpose I/O.
Data direction register D (DDRD) does not affect the data direction of port D pins
that are being used by the SPI module. However, the DDRD bits always
determine whether reading port D returns the states of the latches or the states
of the pins. See Table 12-5.
SS — Slave Select
The PTD0/SS pin is the slave select input of the SPI module. When the SPE bit
is clear, or when the SPI master bit, SPMSTR, is set, the PTD0/SS pin is
available for general-purpose I/O. When the SPI is enabled, the DDRB0 bit in
data direction register B (DDRB) has no effect on the PTD0/SS pin.
12.5.2 Data Direction Register D
Data direction register D (DDRD) determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the
corresponding port D pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0007
Bit 7
DDRD7
0
6
DDRD6
0
5
DDRD5
0
4
DDRD4
0
3
DDRD3
0
2
DDRD2
0
1
DDRD1
0
Figure 12-14. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
MC68HC908GR16 — Rev. 1.0
MOTOROLA
Input/Output Ports (PORTS)
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Data Sheet
139