MC68HC908GR16 Datasheet, PDF (66/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Clock Generator Module (CGM)
9. Calculate and verify the adequacy of the VCO programmed center-of-range
frequency, f_VRS. The center-of-range frequency is the midpoint between the
minimum and maximum frequencies attainable by the PLL.
f_VRS = (L × 2^E)f_NOM
NOTE:
For proper operation,
f_VRS – f_VCLK
≤
-^f-^N----^O----^M------^×-----²---^E--
2
10. Verify the choice of P, R, N, E, and L by comparing f_VCLK to f_VRS and
f_VCLKDES. For proper operation, f_VCLK must be within the application’s
tolerance of f_VCLKDES, and f_VRS must be as close as possible to f_VCLK.
Exceeding the recommended maximum bus frequency or VCO frequency can
crash the MCU.
11. Program the PLL registers accordingly:
a. In the PRE bits of the PLL control register (PCTL), program the binary
equivalent of P.
b. In the VPR bits of the PLL control register (PCTL), program the binary
equivalent of E.
c. In the PLL multiplier select register low (PMSL) and the PLL multiplier
select register high (PMSH), program the binary equivalent of N.
d. In the PLL VCO range select register (PMRS), program the binary
coded equivalent of L.
e. In the PLL reference divider select register (PMDS), program the
binary coded equivalent of R.
Table 4-1 provides numeric examples (numbers are in hexadecimal notation):
Table 4-1. Numeric Example
f_BUS
2.0 MHz
2.4576 MHz
2.5 MHz
4.0 MHz
4.9152 MHz
5.0 MHz
7.3728 MHz
8.0 MHz
f_RCLK
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
32.768 kHz
R
N
P
E
L
1
F5
0
0
D1
1
12C
0
1
80
1
132
0
1
83
1
1E9
0
1
D1
1
258
0
2
80
1
263
0
2
82
1
384
0
2
C0
1
3D1
0
2
D0
Data Sheet
66
Clock Generator Module (CGM)
For More Information On This Product,
Go to: www.freescale.com
MC68HC908GR16 — Rev. 1.0
MOTOROLA