MC68HC908GR16 Datasheet, PDF (272/310 Pages) Motorola, Inc – Microcontrollers

Freescale Semiconductor, Inc.
Development Support
MC68HC908GR16
V_DD
1 µF
1 µF
DB9
2
3
1 _C1+
+
3 _C1–
4 _C2+
+
5 _C2–
7
8
MAX232
V_CC ¹⁶
GND ¹⁵
V+ ²
V– ⁶
10
9
V_DD
+
C5
C3
+
33 pF
N.C.
10 k
15 pF
32.768 kHz
10 MΩ
V_DD
4.7 k
C4
+
74HC125
6
5
74HC125
2
3
4
10 kΩ
RST
OSC2
OSC1
IRQ
PTA0
5
1
V_DD
V_DDA
0.1 µF
PTB4
PTB0
PTB1
PTA1
N.C.
N.C.
N.C.
10 k
V_SSA
V_SS
Figure 19-12. Forced Monitor Mode Circuit (IRQ = GND)
Enter monitor mode with pin configuration shown in Table 19-1 by pulling RST low
and then high. The rising edge of RST latches monitor mode. Once monitor mode
is latched, the values on the specified pins can change.
Once out of reset, the MCU waits for the host to send eight security bytes (see
19.3.2 Security). After the security bytes, the MCU sends a break signal (10
consecutive logic 0s) to the host, indicating that it is ready to receive a command.
19.3.1.1 Normal Monitor Mode
Table 19-1 shows the pin conditions for entering monitor mode.
If V_TST is applied to IRQ and PTB4 is low upon monitor mode entry, the bus
frequency is a divide-by-two of the input clock. If PTB4 is high with V_TST applied to
IRQ upon monitor mode entry, the bus frequency will be a divide-by-four of the
input clock. Holding the PTB4 pin low when entering monitor mode causes a
bypass of a divide-by-two stage at the oscillator only if V_TST is applied to IRQ. In
this event, the CGMOUT frequency is equal to the CGMXCLK frequency, and the
OSC1 input directly generates internal bus clocks. In this case, the OSC1 signal
must have a 50% duty cycle at maximum bus frequency.
When monitor mode was entered with V_TST on IRQ, the computer operating
properly (COP) is disabled as long as V_TST is applied to either IRQ or RST.
Data Sheet
272
Development Support
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MC68HC908GR16 — Rev. 1.0
MOTOROLA