MC68HC08AZ16 Datasheet, PDF (92/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
SIM registers
SIM registers
The SIM has three memory mapped registers. Table 4 shows the
mapping of these registers.
Address
$FE00
$FE01
$FE03
Table 4. SIM Registers
Register
SBSR
SRSR
SBFCR
Access mode
User
User
User
SIM break status
register (SBSR)
The SIM break status register contains a flag to indicate that a break
caused an exit from STOP or WAIT mode.
SBSR
$FE00
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
Bit 0
SBSW
R
R
R
R
R
R
R
Note⁽¹⁾
0
R = Reserved for factory test
1. Writing a logic ’0’ clears SBSW.
Figure 16. SIM break status register (SBSR)
SBSW — SIM Break STOP/WAIT
This status bit is useful in applications requiring a return to STOP or
WAIT mode after exiting from a break interrupt. SBSW can be cleared
by writing a logic ’0’ to it. Reset clears SBSW.
1 = STOP or WAIT mode was exited by break interrupt
0 = STOP or WAIT mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this.
21-sim
MOTOROLA
System Integration Module (SIM)
MC68HC08AZ32
91