MC68HC08AZ16 Datasheet, PDF (157/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
Features
Features of the LVI module include the following:
• Programmable LVI reset
• Programmable power consumption
• Digital filtering of VDD pin level
Functional description
Figure 1 shows the structure of the LVI module. The LVI is enabled out
of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWRD, enables the LVI to monitor
V_DD voltage. The LVI reset bit, LVIRSTD, enables the LVI module to
generate a reset when V_DD falls below a voltage, LVI_TRIPF, and remains
at or below that level for 9 or more consecutive CPU cycles. LVIPWRD
and LVIRSTD are mask options. See Mask Options on page 125 . Once
an LVI reset occurs, the MCU remains in reset until V_DD rises above a
voltage, LVI_TRIPR. V_DD must be above LVI_TRIPR for only one CPU cycle to
bring the MCU out of reset. The output of the comparator controls the
state of the LVIOUT flag in the LVI status register (LVISR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices.
V_DD
LOW V_DD
DETECTOR
LVIPWRD
(FROM MOR)
CPU CLOCK
V_DD > LVI_TRIP = 0
V_DD < LVI_TRIP = 1
V_DD
DIGITAL FILTER
(FROM MOR)
LVIRSTD
LVI RESET
ANLGTRIP
LVIOUT
MC68HC08AZ32
156
Low-Voltage Inhibit (LVI)
2--lvi
MOTOROLA