MC68HC08AZ16 Datasheet, PDF (187/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Communications Interface Module (SCI)
a read of SCDR are required to clear the SCRF bit.
Setting SCRIE enables DMA service so that the DMA
can recognize a service request that occurred during
the error-servicing interrupt routine.
c. In the CPU interrupt routine to service error bits, do not
use BRSET or BRCLR instructions. BRSET and
BRCLR read the SCS1 register, which is the first step in
clearing the register. Then the DMA could read the SCI
data register, the second step in clearing it, thereby
clearing all error bits. The next read of the data register
would miss any error bits that were set.
2. DMA latency should be short enough so that an SCRF is
serviced before the next SCRF occurs. If DMA latency is
long enough for a new SCRF to occur before servicing an
error bit, then:
a. Overruns occur. Set the ORIE bit to enable SCI error
CPU interrupt requests and service the overrun in an
interrupt routine. In a message-based system, disable
the DMA in the interrupt routine and manually recover.
Otherwise, the byte that was lost in the overrun could
prevent the DMA from reaching its byte count. If the
DMA reaches it byte count in the following message,
two messages may be corrupted.
b. If the CPU does not service an overrun interrupt
request, the DMA can eventually clear the SCRF bit by
reading the SCI data register. The OR bit remains set.
Each time a new byte sets the SCRF bit, new data
transfers from the shift register to the SCI data register
(provided that another overrun does not occur), even
though the OR bit is set. The DMA removed the overrun
condition by reading the data register, but the OR bit
has not been cleared.
MC68HC08AZ32
186
Serial Communications Interface Module (SCI)
18-sci
MOTOROLA