MC68HC08AZ16 Datasheet, PDF (517/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Index
memory map . . . . . . . . . . . . . . . . . . . .370
message buffer organization . . . . . . . .354
message buffer outline. . . . . . . . . . . . .371
message storage . . . . . . . . . . . . . . . . .351
module control register (CMCR0) . . . .377
module control register (CMCR1) . . . .379
programmable wake-up function . . . . .366
Receive Error Counter (CRXERR). . . .389
receive structures. . . . . . . . . . . . . . . . .352
receiver flag register (CRFLG). . . . . . .382
receiver interrupt enable register (CRIER).
385
Transmit buffer priority registers (TBPR) . .
375
Transmit Error Counter (CTXERR) . . .390
transmit structures . . . . . . . . . . . . . . . .355
Transmitter Control Register (CTCR) .387
Transmitter Flag Register (CTFLG) . . .386
MSxA/B bits (TIM mode select bits) 266, 268,
289, 292, 464
MSxA/B bits (TIMA mode select bits) . . . 469,
480–481
N
N bit
CCR . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
NEIE bit (SCI noise error interrupt enable bit) .
184, 203
NEIE bit (SCI receiver noise error interrupt en-
able bit). . . . . . . . . . . . . . . . . . . . . .198
NF bit (SCI noise flag bit) . . . . . . . . .184, 203
O
OR bit (SCI receiver overrun bit) . . . .184, 201
ordering information
literature distribution centers . . . . . . . .521
Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . .522
Web server. . . . . . . . . . . . . . . . . . . . . .522
Web site . . . . . . . . . . . . . . . . . . . . . . . .522
ORIE bit (SCI overrun interrupt enable bit) . . .
184
ORIE bit (SCI receiver overrun interrupt en-
able bit). . . . . . . . . . . . . . . . . . . . . .198
OSC1 pin . . . . . . . . . . . . . . . . . . . . . . 17, 107
OSC2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . 17
oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . 152
oscillator enable signal (SIMOSCEN) . . . . 108
oscillator pins
OSC1. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
output compare . . . . . . . . .250, 275, 292, 463
buffered . . . . . . . . . . . . . . . . . . . . 251, 276
unbuffered . . . . . . . . . . . . . . . . . . 250, 275
OVRF bit (SPI overflow bit). . . . . . . . . . . . 241
P
page zero . . . . . . . . . . . . . . . . . . . . . . . . . . 57
parity
SCI module . . . . . . . . . . . . . . . . . 185, 190
PBWC
acquisition mode bit (ACQ) . . . . . . . . . 113
automatic bandwidth control bit (AUTO) . .
112
crystal loss detect bit (XLD). . . . . . . . . 113
lock indicator bit (LOCK) . . . . . . . . . . . 112
PCTL
base clock select bit (BCS) . . . . . . . . . 111
PLL interrupt enable bit (PLLIE) . . . . . 110
PLL interrupt flag bit (PLLF)
PLLF
PCTL110
PLL on bit (PLLON) . . . . . . . . . . . . . . . 111
PE bit (SCI parity error bit) . . . . . . . . . . . . 185
PE bit (SCI receiver parity error bit) . . . . . 203
PEIE bit (SCI parity error interrupt enable bit)
185
PEIE bit (SCI receiver parity error interrupt en-
able bit) . . . . . . . . . . . . . . . . . . . . . 198
PEN bit (SCI parity enable bit) . . . . . . . . . 192
phase-locked loop (PLL) . . . . . . . . . . . 99, 105
acquisition mode . . . . . . . . . .99, 101, 119
acquisition time . . . . . . . . . . . . . . . . . . 119
automatic bandwidth mode . . . . . . . . . 101
lock detector . . . . . . . . . . . . . . . . . . . . 100
loop filter . . . . . . . . . . . . . . . . . . . . . . . 100
manual bandwidth mode . . . . . . . . . . . 112
phase detector. . . . . . . . . . . . . . . . . . . 100
MC68HC08AZ32
516
Index
MOTOROLA