MC68HC08AZ16 Datasheet, PDF (257/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module A (TIMA)
5. In the TIMA status control register (TASC), clear the TIMA
stop bit, TSTOP.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIMA channel 0 registers (TACH0H:TACH0L)
initially control the buffered PWM output. TIMA status control register 0
(TASCR0) controls and monitors the PWM signal from the linked
channels. MS0B takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIMA channel 2 registers (TACH2H:TACH2L)
initially control the PWM output. TIMA status control register 2
(TASCR2) controls and monitors the PWM signal from the linked
channels. MS2B takes priority over MS2A.
Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on
TIMA overflows. Subsequent output compares try to force the output to
a state it is already in and have no effect. The result is a 0% duty cycle
output.
Setting the channel x maximum duty cycle bit (CHxMAX) and clearing
the TOVx bit generates a 100% duty cycle output. See TIMA channel
status and control registers (TASC0–TASC3) on page 264.
MC68HC08AZ32
256
Timer Interface Module A (TIMA)
12-tima
MOTOROLA