MC68HC08AZ16 Datasheet, PDF (430/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

17-appA
MOTOROLA
Appendix A: Related Devices
MC68HC08AZ0
Table 3. Data bus values corresponding to number of WAIT states
External Databus Value
D2 - D0
000
001
010
011
100
101
110
111
Number of WAIT States
0
1
2
3
4
5
6
7
The pin WSCLK provides the T4 signal to synchronize driving the WAIT
state value onto the External Data lines. Table 4 shows the options
available for the WSCLK pin. The WSCLK can also be disabled.
When external WAIT-state decoding is enabled, the low RF emission
data bus freeze function is disabled for data bus lines D2:0. The address
bus freeze function remains unaffected.
Table 4. WSCLK pin function
WSCLK1
0
0
1
1
WSCLK0
0
1
0
1
WSCLK Pin Function
Disabled, tri-state
T4 + CS0, push/pull
T4, push/pull
T4, push/pull
CS0 used in the WSCLK pin functions is active low, irrespective of the
state of the CS0 pin polarity bit. CS0 and WSCLK are not asserted
during internal access bus cycles. The term <T4 + CS0> is therefore an
active low signal.
Examples of external WAIT state selection are shown in Figure 6,
Figure 7 and Figure 5.
Appendix A: Related Devices
MC68HC08AZ32
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