MC68HC08AZ16 Datasheet, PDF (429/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix A: Related Devices
to each address range. The number of WAIT states associated with CS1
address space is determined internally by the CS1WS 1:0 bits.
During T4 the HC08 data bus is not driven and during this clock phase
the number of WAIT states for the cycle in progress is determined. When
CS0 is asserted, the value on the External Data bus at the end of T4 is
used to determine the number of WAIT States according to Table 3 This
WAIT state value is encoded in the first 3 bits of the data bus, D2:0. This
mode of operation is selected by enabling the function in the EBI control
register and by enabling the WSCLK pin according to Table 4 The WAIT
state value on the data bus is only latched when CS0 is asserted.
Therefore, it is not required that the bus be driven during T4 when
accessing addresses outside the CS0 range (i.e. when CS1 is asserted).
The WAIT state value driven onto the External Data bus may be derived
directly from the address lines or indirectly from a decoded chip select
signal(s). In all cases, the WAIT state value must only be allowed to drive
the External Data bus during the period WSCLK is asserted by using a
tri-statable buffer (e.g. 74AC240/244, 74AC367A/368A, 74AC125). See
examples later in this section.
MC68HC08AZ32
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Appendix A: Related Devices
16-appA
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