MC68HC08AZ16 Datasheet, PDF (102/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
Functional description
speed of the lock detector is directly proportional to the final reference
frequency f_RDV. The circuit determines the mode of the PLL and the lock
condition based on this comparison.
Acquisition and
tracking modes
The PLL filter is manually or automatically configurable into one of two
operating modes:
• Acquisition mode — in acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
start-up or when the PLL has suffered a severe noise hit and the
resulting VCO frequency is much different from the desired
frequency. When in acquisition mode, the ACQ bit is clear in the
PLL bandwidth control register. See PLL Bandwidth control
register (PBWC) on page 112
• Tracking mode — in tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. See Base clock selector circuit on page 105 The PLL is
automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.
Manual and
automatic PLL
bandwidth modes
The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically.
In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode is used also to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. See PLL Bandwidth control register (PBWC) on page 112 If
PLL interrupts are enabled, the software can wait for a PLL interrupt
request and then check the LOCK bit. If interrupts are disabled, software
can poll the LOCK bit continuously (during PLL start-up, usually) or at
periodic intervals. In either case, when the LOCK bit is set, the VCO
clock is safe to use as the source for the base clock. See Base clock
selector circuit. If the VCO is selected as the source for the base clock
and the LOCK bit is clear, the PLL has suffered a severe noise hit and
7-cgm
MOTOROLA
Clock Generator Module (CGM)
MC68HC08AZ32
101