MC68HC08AZ16 Datasheet, PDF (205/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Communications Interface Module (SCI)
BKF — Break flag bit
This clearable, read-only bit is set when the SCI detects a break
character on the PTE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request or a DMA
service request. Clear BKF by reading SCS2 with BKF set and then
reading the SCDR. Once cleared, BKF can become set again only
after ’1’s again appear on the PTE1/RxD pin followed by another
break character. Reset clears the BKF bit.
1 = Break character detected
0 = No break character detected
RPF —Reception in progress flag bit
This read-only bit is set when the receiver detects a ’0’ during the RT1
time period of the start bit search. RPF does not generate an interrupt
request. RPF is reset after the receiver detects false start bits (usually
from noise or a baud rate mismatch, or when the receiver detects an
idle character. Polling RPF before disabling the SCI module or
entering STOP mode can show whether a reception is in progress.
1 = Reception in progress
0 = No reception in progress
SCI data register
(SCDR)
The SCI data register is the buffer between the internal data bus and the
receive and transmit shift registers. Reset has no effect on data in the
SCI data register.
SCDR
$0018
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
R7
R6
R5
R4
R3
R2
T7
T6
T5
T4
T3
T2
Unaffected by reset
Figure 11. SCI data register (SCDR)
1
Bit 0
R1
R0
T1
T0
MC68HC08AZ32
204
Serial Communications Interface Module (SCI)
36-sci
MOTOROLA