MC68HC08AZ16 Datasheet, PDF (343/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Ports
Data direction
register G (DDRG)
Data direction register G determines whether each port G pin is an input
or an output. Writing a logic one to a DDRG bit enables the output buffer
for the corresponding port G pin; a logic zero disables the output buffer.
DDRG
$000E
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
DDRG2 DDRG1 DDRG0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 20. Data direction register G (DDRG)
DDRG[2:0] — Data direction register G bits
These read/write bits control port G data direction. Reset clears
DDRG[2:0], configuring all port G pins as inputs.
1 = Corresponding port G pin configured as output
0 = Corresponding port G pin configured as input
NOTE: Avoid glitches on port G pins by writing to the port G data register before
changing data direction register G bits from 0 to 1.
Figure 21 shows the port G I/O logic.
READ DDRG ($000E)
WRITE DDRG ($000E)
RESET
WRITE PTG ($000A)
READ PTG ($000A)
DDRGx
PTGx
Figure 21. Port G I/O circuit
PTGx
MC68HC08AZ32
342
I/O Ports
22-io
MOTOROLA