MC68HC08AZ16 Datasheet, PDF (133/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Break Module
DMA during break
interrupts
During a break interrupt, the DMA is inactive.
If a DMA-generated address matches the contents of the break address
registers, a break interrupt begins at the end of the current CPU
instruction.
If a break interrupt is asserted during the current address cycle and the
DMA is active, the DMA releases the internal address and data buses at
the next address boundary to preserve the current MCU state. During
the break interrupt, the DMA continues to arbitrate DMA channel
priorities. After the break interrupt, the DMA becomes active again and
resumes transferring data according to its highest priority service
request.
TIM and PIT during A break interrupt stops TimerA, TimerB, and the PIT counters.
break interrupts
COP during break The COP is disabled during a break interrupt when V_DD + V_HI is present
interrupts
on the RST pin.
MC68HC08AZ32
132
Break Module
4-brk
MOTOROLA