MC68HC08AZ16 Datasheet, PDF (84/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

System Integration Module (SIM)
Exception control
Exception control
Normal, sequential program execution can be changed in three different
ways:
• Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
• Reset
• Break interrupts
Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents onto the stack and sets the interrupt mask (I-bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume. Figure 7 shows interrupt entry timing, and
Figure 9 shows interrupt recovery timing.
MODULE
INTERRUPT
I-bit
IAB
DUMMY
SP
SP Ð 1 SP Ð 2 SP Ð 3 SP Ð 4 VECT H
VECT L START ADDRESS
IDB
DUMMY ^PCÐ1[7:0] PCÐ1[15:8]
X
A
CCR V DATA H V DATA L OPCODE
R/W
Figure 7. Interrupt entry
13-sim
MOTOROLA
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt may take precedence, regardless of priority,
System Integration Module (SIM)
MC68HC08AZ32
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