MC68HC08AZ16 Datasheet, PDF (110/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
CGM registers
CGM registers
The following registers control and monitor operation of the CGM:
• PLL control register (PCTL). (See PLL control register (PCTL) on
page 110).
• PLL bandwidth control register (PBWC). (See PLL Bandwidth
control register (PBWC) on page 112).
• PLL programming register (PPG). (See PLL Programming register
(PPG) on page 114).
Figure 4 is a summary of the CGM registers.
PCTL
$001C
PBWC
$001D
PPG
$001E
Read:
Write:
Read:
Write:
Read:
Write:
Bit 7
PLLIE
AUTO
MUL7
6
5
4
PLLF
PLLON BCS
LOCK
ACQ
XLD
MUL6 MUL5 MUL4
3
1
0
VRS7
2
1
0
VRS6
1
1
0
VRS5
Bit 0
1
0
VRS4
= Unimplemented
NOTES:
1. When AUTO = 0, PLLIE is forced to logic zero and is read-only.
2. When AUTO = 0, PLLF and LOCK read as logic zero.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS[7:4] = $0, BCS is forced to logic zero and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 4. CGM I/O Register Summary
15-cgm
MOTOROLA
Clock Generator Module (CGM)
MC68HC08AZ32
109