MC68HC08AZ16 Datasheet, PDF (428/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix A: Related Devices
MC68HC08AZ0
0000
CS0 (4K)
and
Internal
0000
CS0 (4K)
and
Internal
0000
CS0 (4K)
and
Internal
0000
CS0 (4K)
and
Internal
1000
CS1 (60K)
1000
CS0 (12K)
4000
1000
CS0 (28k)
8000
1000
CS0 (44K)
FFFF
CS1 (48K)
FFFF
CS1 (32K)
FFFF
C000
CS1 (16K)
FFFF
Figure 5. Software controlled chip-select combinations
$1000 without the use of an external decoder (the CS0 pin would
otherwise be redundant). Internal accesses will always have priority.
When a chip-select is enabled, it is active for all memories and I/O cycles
within its defined (external) area. Each chip-select has control bits for
enabling, polarity setting and for inserting the correct number of WAIT
states in each bus cycle. Out of reset CS0 and CS1 are configured with
the maximum number (3) of software controlled WAIT states.
All bus timing interface signals are handled by the bus timing interface
logic that generates the proper signals for reads and writes required to
interface the internal and external buses.
Externally
controlled WAIT
states
The EBI generates an IWS signal which can be controlled either
internally or externally for CS0. The external option allows the user to
further decode the CS0 address space into smaller address ranges for
multiple external devices, and assign a different number of WAIT states
15-appA
MOTOROLA
Appendix A: Related Devices
MC68HC08AZ32
427