MC68HC08AZ16 Datasheet, PDF (115/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
PLL Programming
register (PPG)
The PLL programming register contains the programming information
for the modulo feedback divider and the programming information for the
hardware configuration of the VCO.
PPG
$001E
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
MUL7 MUL6 MUL5 MUL4 VRS7 VRS6
0
1
1
0
0
1
Figure 8. PLL Programming register (PPG)
1
VRS5
1
Bit 0
VRS4
0
MUL[7:4] — Multiplier select bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier, N. (See PLL circuits on page 100 and
Programming the PLL on page 103). A value of $0 in the multiplier
select bits configures the modulo feedback divider the same as a
value of $1. Reset initializes these bits to $6 to give a default multiply
value of 6.
Table 7. VCO frequency multiplier (N) selection
MUL7:MUL6:MUL5:MUL4
0000
0001
0010
0011
VCO Frequency Multiplier (N)
1
1
2
3
1101
13
1110
14
1111
15
NOTE: The multiplier select bits have built-in protection that prevents them from
being written when the PLL is on (PLLON = 1).
MC68HC08AZ32
114
Clock Generator Module (CGM)
20-cgm
MOTOROLA