MC68HC08AZ16 Datasheet, PDF (124/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
Acquisition/lock time specifications
cycles, n_ACQ, is required to ascertain whether the PLL is within the
tracking mode entry tolerance ∆_TRK, before exiting acquisition mode.
Also, a certain number of clock cycles, n_TRK, is required to ascertain
whether the PLL is within the lock mode entry tolerance ∆_LOCK.
Therefore, the acquisition time t_ACQ, is an integer multiple of n_ACQ/f_RDV,
and the acquisition to lock time t_AL, is an integer multiple of n_TRK/f_RDV.
Also, since the average frequency over the entire measurement period
must be within the specified tolerance, the total time usually is longer
than t_LOCK as calculated above.
In manual mode, it is usually necessary to wait considerably longer than
t_LOCK before selecting the PLL clock (see Base clock selector circuit on
page 105), because the factors described in Parametric influences on
reaction time on page 120 may slow the lock time considerably.
Table 8. CGM component specifications
Characteristic
Symbol Min
Typ.
Max
Notes
Crystal load capacitance
C_L
–
Crystal fixed capacitance
C_f
–
Crystal tuning
capacitance
C₂
–
2 * C_L
2 * C_L
– Consult crystal mfg. data
– Consult crystal mfg. data
– Consult crystal mfg. data
Feedback bias resistor
R_B
–
Series resistor
R_S
0
22MΩ
330kΩ
–
1M
Ω
Not required
Filter capacitor
Filter capacitor multiply
factor
C_F
C_FACT
– C_FACT * (V_DDA / f_XCLK) –
–
0.0154 F/sV
–
F/sV
Bypass capacitor
C_BYP
–
0.1 µF
C_BYP must provide low
AC impedance from f =
– f_XCLK/100 to 100 *f_XCLK ,
so series resistance
must be considered
29-cgm
MOTOROLA
Clock Generator Module (CGM)
MC68HC08AZ32
123