MC68HC08AZ16 Datasheet, PDF (159/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Low-Voltage Inhibit (LVI)
LVI Status Register (LVISR)
The LVI status register flags V_DD voltages below the LVI_TRIPF level.
Bit 7
6
5
4
3
2
LVISR ^{Read: LVIOUT}
0
0
0
0
0
$FE0F _Write:
Reset: 0
0
0
0
0
0
= Unimplemented
Figure 2. LVI Status Register (LVISR)
1
Bit 0
0
0
0
0
LVIOUT — LVI Output Bit
This read-only flag becomes set when V_DD falls below the LVI_TRIPF
voltage for 32-40 CGMXCLK cycles. (See Table 2). Reset clears the
LVIOUT bit.
Table 2. LVIOUT bit indication
at level:
V_DD > LVI_TRIPR
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
V_DD < LVI_TRIPF
LVI_TRIPF < V_DD < LVI_TRIPR
V_DD
for number of CGMXCLK
cycles:
ANY
< 32 CGMXCLK cycles
between 32 & 40 CGMXCLK
cycles
> 40 CGMXCLK cycles
ANY
LVIOUT
0
0
0 or 1
1
Previous Value
MC68HC08AZ32
158
Low-Voltage Inhibit (LVI)
4-lvi
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