MC68HC08AZ16 Datasheet, PDF (103/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
the software must take appropriate action, depending on the application.
(See Interrupts on page 116 for information and precautions on using
interrupts). The following conditions apply when the PLL is in automatic
bandwidth control mode:
• The ACQ bit (see PLL Bandwidth control register (PBWC) on
page 112) is a read-only indicator of the mode of the filter, see
Acquisition and tracking modes on page 101.
• The ACQ bit is set when the VCO frequency is within a certain
tolerance ∆_TRK and is cleared when the VCO frequency is outwith
a certain tolerance ∆_UNT. (See Acquisition/lock time specifications
on page 119).
• The LOCK bit is a read-only indicator of the locked state of the
PLL.
• The LOCK bit is set when the VCO frequency is within a certain
tolerance ∆_LOCK and is cleared when the VCO frequency is outwith
a certain tolerance ∆_UNL. (See Acquisition/lock time specifications
on page 119).
• CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. (See PLL control
register (PCTL) on page 110).
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below f_BUSMAX
and require fast start-up. The following conditions apply when in manual
mode:
• ACQ is a writeable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
• Before entering tracking mode (ACQ = 1), software must wait a
given time, t_ACQ (see Acquisition/lock time specifications on page
119), after turning on the PLL by setting PLLON in the PLL control
register (PCTL).
MC68HC08AZ32
102
Clock Generator Module (CGM)
8-cgm
MOTOROLA