MC68HC08AZ16 Datasheet, PDF (109/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
NOTE:
To prevent noise problems, C_F should be placed as close to the
CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the C_F connection.
PLL analog power
pin (V_DDA)
NOTE:
V_DDA is a power pin used by the analog portions of the PLL. The pin
should be connected to the same voltage potential as the V_DD pin.
Route V_DDA carefully for maximum noise immunity and place bypass
capacitors as close as possible to the package.
Oscillator enable The SIMOSCEN signal comes from the system integration module (SIM)
signal (SIMOSCEN) and enables the oscillator and PLL.
Crystal output
frequency signal
(CGMXCLK)
CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f_XCLK) and is generated directly from the crystal oscillator
circuit. Figure 1 shows only the logical relation of CGMXCLK to OSC1
and OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at start-up.
CGM base clock
output (CGMOUT)
CGMOUT is the clock output of the CGM. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50% duty cycle clock
running at twice the bus frequency. CGMOUT is software programmable
to be either the oscillator output (CGMXCLK) divided by two or the VCO
clock (CGMVCLK) divided by two.
CGM CPU interrupt CGMINT is the interrupt signal generated by the PLL lock detector.
(CGMINT)
MC68HC08AZ32
108
Clock Generator Module (CGM)
14-cgm
MOTOROLA