MC68HC08AZ16 Datasheet, PDF (120/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
Acquisition/lock time specifications
Acquisition/lock time specifications
The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.
Acquisition/lock
time definitions
25-cgm
MOTOROLA
Typical control systems refer to the acquisition time or lock time as the
reaction time of the system, within specified tolerances, to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percentage of
the step input or when the output settles to the desired value plus or
minus a percentage of the frequency change. Therefore, the reaction
time is constant in this definition, regardless of the size of the step input.
For example, consider a system with a 5% acquisition time tolerance. If
a command instructs the system to change from 0Hz to 1MHz, the
acquisition time is the time taken for the frequency to reach 1MHz ±
50kHz. 50kHz = 5% of the 1MHz step input. If the system is operating at
1MHz and suffers a –100kHz noise hit, the acquisition time is the time
taken to return from 900kHz to 1MHz ± 5kHz. 5kHz = 5% of the 100kHz
step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are as follows:
• Acquisition time, t_ACQ, is the time the PLL takes to reduce the error
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance ∆_TRK.
Acquisition time is based on an initial frequency error, (f_DES –
Clock Generator Module (CGM)
MC68HC08AZ32
119