MC68HC08AZ16 Datasheet, PDF (491/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix C: ADC-15
ADC Port I/O Pins
PTD6/TACLK-PTD0 and PTB7/ATD7-PTB0/ATD0 are general-purpose
I/O pins that share with the ADC channels.
The channel select bits define which ADC channel/port pin will be used
as the input signal. The ADC overrides the port I/O logic by forcing that
pin as input to the ADC. The remaining ADC channels/port pins are
controlled by the port I/O logic and can be used as general-purpose I/O.
Writes to the port register or DDR will not have any affect on the port pin
that is selected by the ADC. Read of a port pin which is in use by the
ADC will return a logic 0 if the corresponding DDR bit is at logic 0. If the
DDR bit is at logic 1, the value in the port data latch is read.
NOTE:
Do not use ADC channels ATD14 or ATD12 when using the
PTD6/TACLK or PTD4/TBLCK pins as the clock inputs for the 16-bit
Timers.
Voltage
Conversion
NOTE:
When the input voltage to the ADC equals V_REFH (see ADC
Characteristics on page 398), the ADC converts the signal to $FF (full
scale). If the input voltage equals V_SSA, the ADC converts it to $00. Input
voltages between V_REFH and V_SSA are a straight-line linear conversion.
All other input voltages will result in $FF if greater than V_REFH and $00 if
less than V_SSA.
Input voltage should not exceed the analog supply voltages.
Conversion Time
Conversion starts after a write to the ADSCR (ADC status control
register, $0038), and requires between 16 and 17 ADC clock cycles to
complete. Conversion time in terms of the number of bus cycles is a
function of ADICLK select, CGMXCLK frequency, bus frequency, and
ADIV prescaler bits. For example, with a CGMXCLK frequency of 4
MHz, bus frequency of 8 MHz, and fixed ADC clock frequency of 1 MHz,
one conversion will take between 16 and 17 µs and there will be between
128 bus cycles between each conversion. Sample rate is approximately
60 kHz.
MC68HC08AZ32
490
Appendix C: ADC-15
4-adc15
MOTOROLA