MC68HC08AZ16 Datasheet, PDF (499/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix C: ADC-15
Table 2. ADC Clock Divide Ratio
ADIV2 ADIV1
0
0
0
0
0
1
0
1
1
X
X = don’t care
ADIV0
0
1
0
1
X
ADC Clock Rate
ADC Input Clock /1
ADC Input Clock / 2
ADC Input Clock / 4
ADC Input Clock / 8
ADC Input Clock / 16
ADICLK — ADC Input Clock Register Bit
ADICLK selects either bus clock or CGMXCLK as the input clock
source to generate the internal ADC clock. Reset selects CGMXCLK
as the ADC clock source.
If the external clock (CGMXCLK) is equal to or greater than 1 MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1 MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at
approximately 1 MHz, correct operation can be guaranteed. See ADC
Characteristics on page 398.
1 = Internal bus clock
0 = External clock (CGMXCLK)
1 MHz = ^fX^CL^K ^or ^Bu^s ^Fr^eq^ue^nc^y
ADIV[2:0]
NOTE: During the conversion process, changing the ADC clock will result in an
incorrect conversion.
MC68HC08AZ32
498
Appendix C: ADC-15
12-adc15
MOTOROLA