MC68HC08AZ16 Datasheet, PDF (312/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Analog-to-Digital Converter (ADC)
I/O registers
ADC data register One 8-bit result register is provided. This register is updated each time
(ADR)
an ADC conversion completes.
ADR
$0039
Read:
Write:
Reset:
Bit 7
AD7
0
6
AD6
5
AD5
0
0
= Unimplemented
4
AD4
0
3
AD3
0
2
AD2
0
1
AD1
0
Bit 0
AD0
0
Figure 3. ADC data register
ADC clock register This register selects the clock frequency for the ADC
(ADCLKR)
Bit 7
6
5
4
3
2
ADCLK
$003A
Read:
Write:
ADIV2
ADIV1
ADIV0 ADICLK
0
0
Reset: 0
0
0
0
0
0
= Unimplemented
Figure 4. ADC clock register
1
Bit 0
0
0
0
0
ADIV2:ADIV0 - ADC clock prescaler bits
ADIV2, ADIV1and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 2
shows the available clock configurations. The ADC clock should be
set to approximately 1MHz.
cgmxclk or bus frequency
1MHz =
ADIV [2:0]
11-adc
MOTOROLA
Analog-to-Digital Converter (ADC)
MC68HC08AZ32
311