MC68HC08AZ16 Datasheet, PDF (266/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Timer Interface Module A (TIMA)
I/O registers
CHxF— Channel x Flag Bit
When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIMA
counter registers matches the value in the TIMA channel x registers.
When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIMA channel x status and control register with
CHxF set and then writing a logic zero to CHxF. If another interrupt
request occurs before the clearing sequence is complete, then writing
logic zero to CHxF has no effect. Therefore, an interrupt request
cannot be lost due to inadvertent clearing of CHxF.
Reset clears the CHxF bit. Writing a logic one to CHxF has no effect.
1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x
CHxIE — Channel x Interrupt Enable Bit
This read/write bit enables TIMA CPU interrupts on channel x.
Reset clears the CHxIE bit.
1 = Channel x CPU interrupt requests enabled
0 = Channel x CPU interrupt requests disabled
MSxB — Mode Select Bit B
This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIMA channel 0 and TIMA channel 2 status
and control registers.
Setting MS0B disables the channel 1 status and control register and
reverts TCH1B to general-purpose I/O.
Setting MS2B disables the channel 3 status and control register and
reverts TCH3B to general-purpose I/O.
Reset clears the MSxB bit.
1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled
21-tima
MOTOROLA
Timer Interface Module A (TIMA)
MC68HC08AZ32
265