MC68HC08AZ16 Datasheet, PDF (435/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix A: Related Devices
Choosing to drive different addresses onto the data bus during T4 allows
the user to provide a different mix of WAIT states throughout the
decoded CS0 address space. Alternatively, the 3-8 line decoder could
be replaced with a PAL which would provide for a more complex decode
and assignment of WAIT states. The number of WAIT states for CS1 is
selected internally based on the contents of CS1WS1:0 bits and may
between 0 and 3 bus cycles.
EBI control
registers
The following I/O registers control and monitor operation of the EBI:-
• EBI Control Register (EBIC)
• Chip-Select Control Register (EBICS)
EBI control register
EBIC ^Read:
$003B _Write:
Reset
:
Bit 7
0
6
5
4
3
2
1
IRV
MODE C0WS WSCLK1 WSCLK0 CSC1
0
0
0
0
0
0
0
= Unimplemented
Figure 9. EBI control register (EBIC)
0
CSC0
0
IRVIRV - Internal read visibility bit
This function is included for easy-debug of the customer application.
1 = The REB and WEB are active during IRV, to allow creation of
an ECLK. Enabled chip selects are active as well, and all
internal bus activity is externally visible.
0 = In normal user operation IRV should be off to prevent possible
bus contention.
MC68HC08AZ32
434
Appendix A: Related Devices
22-appA
MOTOROLA