MC68HC08AZ16 Datasheet, PDF (520/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Index
SPTIE bit (SPI transmitter interrupt enable
bit). . . . . . . . . . . . . . . . . . . . . . . . . .239
SPWOM bit (SPI wired-OR mode bit)234, 238
SRSR
computer operating properly reset bit
(COP) . . . . . . . . . . . . . . . . . . . . .93
external reset bit (PIN) . . . . . . . . . . . . . .92
illegal address reset bit (ILAD). . . . . . . .93
illegal opcode reset bit (ILOP) . . . . . . . .93
low-voltage inhibit reset bit (LVI) . . . . . .93
power-on reset bit (POR) . . . . . . . . . . . .92
SSREC
MORA . . . . . . . . . . . . . . . . . . . . . . . . .126
stack pointer . . . . . . . . . . . . . . . . . . . . . . . .37
stack pointer (SP) . . . . . . . . . . . . . . . . . . . .56
stack RAM . . . . . . . . . . . . . . . . . . . . . . .37, 57
start bit. . . . . . . . . . . . . . . . . . . . . . . .142, 175
SCI data . . . . . . . . . . . . . . . . . . . . . . . .192
stop bit. . . . . . . . . . . . . . . . . . . . . . . . . . . .175
SCI data . . . . . . . . . . . . . . . . . . . .185, 191
STOP bit (STOP enable bit) . . . . . . . . . . .154
STOP instruction 90, 117, 135, 152, 154, 159,
187, 232, 295, 471, 492
STOP mode. . . . . . . . . . . . . . . . . . . .306, 492
entry timing . . . . . . . . . . . . . . . . . . . . . .90
recovery from interrupt break. . . . . . . . .90
stop mode . . . . . . . . .151, 159, 204, 295, 471
recovery time . . . . . . . . . . . . . . . . . . . . .76
SWI instruction . . . . . . . . . . .60, 86, 131, 140
system inegration module (SIM)
STOP mode . . . . . . . . . . . . . . . . . . . . . .89
system integration module (SIM). . . . . .72, 93
break flag control register (SBFCR). . . .93
break status register (SBSR) . . . . . . . . .91
exception control . . . . . . . . . . . . . . . . . .83
reset status register (SRSR) . . . . .92, 151
SIM counter . . . . . . . . . . . . . .82, 151–152
WAIT mode . . . . . . . . . . . . . . . . . . . . . .88
T
T8 bit (SCI transmitted bit 8) . . . . . . . . . . .197
T8 bit (transmitted SCI bit 8) . . . . . . . . . . .174
TCIE bit (SCI transmission complete interrupt
enable bit) . . . . . . . . . . . . . . . . . . . 194
TE bit (SCI transmitter enable bit). . . . . . . 195
TE bit (transmitter enable bit) . . . . . . . . . . 175
thermal characteristics . . . . . . . . . . . . . . . 395
TIMA counter . . . . . . . . . . . . . . . . . . . . . . 258
timer interface module (TIM). . . . . . . . . . . 292
channel registers (TCH0H/L–TCH3H/L) . .
292
prescaler . . . . . . . . . . . . . . . . . . . . . . . 461
timer interface module (TIMA)
channel registers
(TACH0H/L–TACH3H/L). . . . . . 268
channel status and control registers
(TASC0–TASC3) . . . . . . . . . . . 264
clock input pin (PTD3/TACLK). . . . . . . 259
clock input pin (PTD6/ATD14/TCLK). . 473
counter modulo registers
(TAMODH:TAMODL) . . . . . . . . 263
counter registers (TACNTH/L). . .262–263
prescaler . . . . . . . . . . . . . . . . . . . . . . . 249
status and control register (TASC) . . 260,
469, 474
timer interface module (TIMA-6)
channel I/O pins (PTF3-PTF0/TACH2 and
PTE3/TACH1-PTE2/TACH0) . . 473
channel registers
(TACH0H/L–TACH3H/L). 464–465,
473, 483
channel status and control registers
(TASC0–TASC3) . . . . . . . 464, 478
counter modulo registers (TAMODH/L) . . .
477
counter modulo registers
(TAMODH:TAMODL) . . . . . . . . 469
counter registers (TACNTH/L). . . . . . . 476
counter registers (TACNTH:TACNTL). 476
status and control register (TASC) . . 461,
474
timer interface module (TIMB)
channel registers
(TBCH0H/L–TBCH3H/L). . . . . . 292
channel status and control registers
(TBSC0–TBSC1) . . . . . . . . . . . 288
MOTOROLA
Index
MC68HC08AZ32
519