MC68HC08AZ16 Datasheet, PDF (216/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Serial Peripheral Interface Module (SPI)
Functional description
MASTER MCU
SHIFT REGISTER
BAUD RATE
GENERATOR
MISO
MOSI
SPSCK
SS
SLAVE MCU
MISO
MOSI
SPSCK
SHIFT REGISTER
SS
V_DD
Figure 3. Full-duplex master-slave connections
Slave mode
7-spi
MOTOROLA
The SPI operates in slave mode when the SPMSTR bit is clear. In slave
mode the SPSCK pin is the input for the serial clock from the master
MCU. Before a data transmission occurs, the SS pin of the slave MCU
must be at ‘0’. SS must remain low until the transmission is complete.
See Mode fault error on page 224.
In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it transfers to the receive data register, and the
SPRF bit is set. To prevent an overflow condition, slave software must
then read the SPI data register before another byte enters the shift
register.
The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed (which is twice as fast as the fastest master
SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any
particular SPI baud rate. The baud rate only controls the speed of the
SPSCK generated by an SPI configured as a master. Therefore, the
frequency of the SPSCK for an SPI configured as a slave can be any
frequency less than or equal to the bus speed.
A slave SPI must complete the write to the data register at least one bus
cycle before the master SPI starts a transmission. When the clock phase
bit (CPHA) is set, the first edge of SPSCK starts a transmission. When
Serial Peripheral Interface Module (SPI)
MC68HC08AZ32
215