MC68HC08AZ16 Datasheet, PDF (333/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

I/O Ports
DDRD bits always determine whether reading port D returns the states
of the latches to logic 0.
TACLK/TBCLK — Timer clock input
The PTD6/TACLK pin is the external clock input for the TIMA. The
PTD4/TBCLK pin is the external clock input for the TIMB.The
prescaler select bits, PS[2:0], select PTD6/TACLK or PTD4/TBCLK
as the TIM clock input (see TIMA channel status and control registers
(TASC0–TASC3) on page 264 and TIMB status and control register
(TBSC) on page 284). When not selected as the TIM clock,
PTD6/TAClk and PTD4/TBCLK are available for general purpose I/O.
While TACLK/TBCLK are selected, corresponding DDRD bits have
no effect.
Data direction
register D (DDRD)
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic one to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic zero disables the output buffer.
DDRD
$0007
Bit 7
6
5
4
3
2
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2
Write:
Reset: 0
0
0
0
0
0
Figure 11. Data direction register D (DDRD)
1
DDRD1
0
Bit 0
DDRD0
0
DDRD[7:0] — Data direction register D bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
Figure 12 shows the port D I/O logic.
When bit DDRDx is a logic one, reading address $0003 reads the PTDx
data latch. When bit DDRDx is a logic zero, reading address $0003
MC68HC08AZ32
332
I/O Ports
12-io
MOTOROLA