MC68HC08AZ16 Datasheet, PDF (113/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
PLL Bandwidth
control register
(PBWC)
The PLL bandwidth control register does the following:
• Selects automatic or manual (software-controlled) bandwidth
control mode
• Indicates when the PLL is locked
• In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
• In manual operation, forces the PLL into acquisition or tracking
mode
Bit 7
6
5
4
3
2
1
Bit 0
PBWC
$001D
Read:
Write:
AUTO
LOCK
ACQ
XLD
0
0
0
0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 7. PLL bandwidth control register (PBWC)
AUTO — Automatic bandwidth control bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), the ACQ
bit should be cleared before turning the PLL on. Reset clears the
AUTO bit.
1 = Automatic bandwidth control
0 = Manual bandwidth control
LOCK — Lock indicator bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
‘0’ and has no meaning. Reset clears the LOCK bit.
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
MC68HC08AZ32
112
Clock Generator Module (CGM)
18-cgm
MOTOROLA