MC68HC08AZ16 Datasheet, PDF (111/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
PLL control register The PLL control register contains the interrupt enable and flag bits, the
(PCTL)
on/off switch, and the base clock selector bit.
PCTL
$001C
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
PLLF
1
1
PLLIE
PLLON BCS
0
0
1
0
1
1
= Unimplemented
Figure 5. PLL control register (PCTL)
1
Bit 0
1
1
1
1
PLLIE — PLL interrupt enable bit
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as ‘0’. Reset clears the PLLIE bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
PLLF — PLL interrupt flag bit
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit is set also. PLLF
always reads as ‘0’ when the AUTO bit in the PLL bandwidth control
register (PBWC) is clear. The PLLF bit should be cleared by reading
the PLL control register. Reset clears the PLLF bit.
1 = Change in lock condition
0 = No change in lock condition
NOTE:
The PLLF bit should not be inadvertently cleared. Any read or
read-modify-write operation on the PLL control register clears the PLLF
bit.
MC68HC08AZ32
110
Clock Generator Module (CGM)
16-cgm
MOTOROLA