MC68HC08AZ16 Datasheet, PDF (498/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Appendix C: ADC-15
I/O Registers
ADC Data Register One 8-bit result register is provided. This register is updated each time
an ADC conversion completes.
Bit 7
6
5
4
3
2
1
Bit 0
ADR ^{Read: AD7}
AD6
AD5
AD4
AD3
AD2
AD1
AD0
$0039 _{Write: R}
R
R
R
R
R
R
R
Reset:
Indeterminate after Reset
R = Reserved
Figure 3. ADC Data Register (ADR)
ADC Input Clock
Register
This register selects the clock frequency for the ADC.
Bit 7
6
5
4
3
2
1
Bit 0
ADC
$003A
Read:
ADIV2
Write:
ADIV1
ADIV0 ADICLK
0
R
0
R
0
R
0
R
Reset: 0
0
0
0
0
0
0
0
R = Reserved
Figure 4. ADC Input Clock Register (ADICLK)
ADIV2–ADIV0 — ADC Clock Prescaler Bits
ADIV2, ADIV1, and ADIV0 form a 3-bit field which selects the divide
ratio used by the ADC to generate the internal ADC clock. Table 2
shows the available clock configurations. The ADC clock should be
set to approximately 1 MHz.
11-adc15
MOTOROLA
Appendix C: ADC-15
MC68HC08AZ32
497