MC68HC08AZ16 Datasheet, PDF (168/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

External Interrupt Module (IRQ)
IRQ status and control register (ISCR)
IRQ1F — IRQ1 flag
This read-only status bit is high when the IRQ1 interrupt is pending.
1 = Interrupt pending
0 = Interrupt not pending
ACK1 — IRQ1 interrupt request acknowledge bit
Writing a ’1’ to this write-only bit clears the IRQ1 latch. ACK1 always
reads as ’0’. Reset clears ACK1.
IMASK1 — IRQ1 Interrupt mask bit
Writing a ’1’ to this read/write bit disables IRQ1 interrupt requests.
Reset clears IMASK1.
1 = IRQ1 interrupt requests disabled
0 = IRQ1 interrupt requests enabled
MODE1 — IRQ1 edge/level select bit
This read/write bit controls the triggering sensitivity of the IRQ1/V_PP
pin. Reset clears MODE1.
1 = Interrupt requests on falling edges and low levels
0 = Interrupt requests on falling edges only
7-irq
MOTOROLA
External Interrupt Module (IRQ)
MC68HC08AZ32
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