MC68HC08AZ16 Datasheet, PDF (100/527 Pages) Motorola, Inc – HCMOS Microcontroller Unit

Clock Generator Module (CGM)
Functional description
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
PLLF
1
1
1
1
PLL Control Register (PCTL) PLLIE
PLLON BCS
LOCK
0
0
0
0
PLL Bandwidth Control Register (PBWC) AUTO
ACQ XLD
PLL Programming Register (PPG) MUL7 MUL6 MUL5 MUL4 VRS7 VRS6 VRS5 VRS4
= Unimplemented
Figure 2. CGM I/O register summary
Crystal oscillator
circuit
The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) enables the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components.
An externally generated clock can also feed the OSC1 pin of the crystal
oscillator circuit. For this configuration, the external clock should be
connected to the OSC1 pin and the OSC2 pin allowed to float.
Phase-locked
loop (PLL) circuit
The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.
5-cgm
MOTOROLA
Clock Generator Module (CGM)
MC68HC08AZ32
99